A self-aligned contact is essential for 14 nm technology nodes to eliminate massive polysilicon gate electrode (PC) to source/drain contact (CA) short for sub 64 nm CPP devices. The self-aligned contact is usually realized by implementing a silicon nitride (SiN), a silicon carbon nitride (SiCN), or a silicon boron carbon nitride (SiBCN) cap material on top of the gate electrode to act as a contact etch stop layer. However, the gate stack is particularly sensitive to cap process conditions, which often result in threshold voltage (Vt) shift up to 300 millivolts (mV) for p-channel field-effect transistors (PFETs) or Vt roll-up issues for n-channel field-effect transistors (NFETs).
A need therefore exists for a methodology enabling formation of a dielectric cap without Vt shift or Vt roll-up, and the resulting device.